Input/Output core (I/O) designers physically design their I/O's to pack the most connections between the IC and the package in the smallest amount of area. Over time, IC interfaces have become a limiting factor, as many packages require the chip I/O's to be surrounding the functional area of the IC along the outer edges of the die. Unfortunately, area grows faster than the length of the periphery of the die. For instance, when comparing a die that is one cm on a side to a die that is two cm on a side, the two cm die will have roughly four times the area for logic (four square centimeters versus one square centimeter) but only two times the periphery for I/O (8 cm versus 4 cm). Because of this, I/O's have tended to be physically designed tall and skinny—the narrower the better—to maximize the number of connections possible in the same amount of length along the perimeter of the die.
The tall and skinny I/O layout requires the I/O be rotated 90 degrees for placement along the sides of the die, and 180 degrees for placement along the top of the die. Of recent, however, process design rules have added constraints to the physical layout of the transistors on a die, one of which is that all transistor gates must be oriented in the same direction (e.g., vertical). It is difficult, however, to accommodate these constraints. For example, the orientation constraint can be accommodated by designing a special I/O layout for each side of the die, one that has the tall and skinny layout with the transistors similarly oriented. This is undesirable because of the time and expense required to do such. Alternatively, the orientation constraint can be accommodated by not rotating the I/O by 90 degrees along the sides of the design, thereby effectively making the I/O short and fat along the sides, and thereby reducing the number of I/O's surrounding the chip. This is undesirable for obvious reasons.
Accordingly, what is needed in the art is an I/O design that addresses the problems experienced by current I/O designs, including one that accommodates the need for symmetric transistor layout, while maintaining or even improving I/O packing density.